PRELIMINARY
FIMV-MFC V1.0
MULTI-FORMAT
VIDEO
CODEC
2
1-39
Preliminary product information describe products that are in development,
for which full characterization data and associated errata are not yet available.
Specifications and information herein are subject to change without notice.
Block diagram
The figure 21.30 highlights the overlap/deblocking filter architecture. The filtered pixel data are stored in working
buffer. The output data is store to output buffer. The rotator/mirror block will read this output buffer. The input
buffer and DMA buffer is used to store/load the intermediate data for processing deblock/overlap filter.
Read/Write DMA
top_ctrl
AXI
ipbus
SDRAM
output buffer
dpreg64x40
input buffer
dpreg96x40
overlap/
deblock
working buffer
spreg272x44
Recon
buffer
deblock
output
output buffer
spreg272x44
Figure 21.30
The main controller (top_ctrl) is controlled through ip-bus by BIT processor. The BIT processor writes control
information (processing mode, filter mode (H.263/H.264/MPEG-4/VC-1), run command etc.) into the control
register in main controller.
Overlap-smoothing filter is enabled in VC-1 mode. In VC-1 mode, overlap-smoothing filtering is processed before
deblocking filter. Deblock/overlap-smoothing filter reads the data to filter from reconstructed buffer. In stand-alone
mode, the reconstructed data is loaded from SDRAM. Deblock/overlap-smoothing filter uses working buffer as
temporal working buffer for filtering process. After filtering process is finished, the output data is moved to output
buffer for next pipe-line stage. For filtering macroblock edge, the neighbor macroblock data is stored in working
buffer.