PRELIMINARY
HSMMC CONTROLLER
S3C6400X RISC MICROPROCESSOR
27-66
Preliminary product information describe products that are in development,
for which full characterization data and associated errata are not yet available.
Specifications and information herein are subject to change without notice.
CONTROL REGISTER 3 REGISTER
Register
Address
R/W
Description
Reset Value
CONTROL3_0 0x7C200084 R/W
FIFO Interrupt Control (Control Register 3)
(Channel 0)
0x7F5F3F1F
CONTROL3_1 0x7C300084 R/W
FIFO Interrupt Control (Control Register 3)
(Channel 1)
0x7F5F3F1F
CONTROL3_2 0x7C400084 R/W
FIFO Interrupt Control (Control Register 3)
(Channel 2)
0x7F5F3F1F
Name
Bit
Description
Initial Value
FCSel3 [31]
Feedback Clock Select [3]
Reference Note (1)
0x0
FIA3 [30:24]
FIFO Interrupt Address register 3
FIFO (512Byte Buffer memory, word address unit)
Initial value(0x7F) generates at 512-byte(128-word) position.
0x7F
FCSel2 [23]
Feedback Clock Select [2]
Reference Note (1)
0x0
FIA2 [22:16]
FIFO Interrupt Address register 2
FIFO (512Byte Buffer memory, word address unit)
Initial value(0x5F) generates at 384-byte(96-word) position.
0x5F
FCSel1 [15]
Feedback Clock Select [1]
Reference Note (2)
0x0
FIA1 [14:8]
FIFO Interrupt Address register 1
FIFO (512Byte Buffer memory, word address unit)
Initial value(0x3F) generates at 256-byte(64-word) position.
0x3F
FCSel0 [7]
Feedback Clock Select [0]
Reference Note (2)
0x0
FIA0 [6:0]
FIFO Interrupt Address register 0
FIFO (512Byte Buffer memory, word address unit)
Initial value(0x1F) generates at 128-byte(32-word) position.
0x1F
Note (1):
FCSel[3:2] : Tx Feedback Clock Delay Control
‘01’=Delay1 (less delay), ‘11’=Delay2, ‘00’=Delay3, ‘10’=Delay4 (more delay)
Note (2):
FCSel[1:0] : Rx Feedback Clock Delay Control
‘00’=Delay1 (less delay), ‘01’=Delay2, ‘10’=Delay3, ‘11’=Delay4 (more delay)