PRELIMINARY
S3C6400X RISC MICROPROCESSOR
SYSTEM CONTROLLER
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SYSTEM CONTROLLER
OVERVIEW
The System Controller consists of two parts; System Clock Control and System Power-management Control. The
System Clock Control logic in S3C6400 can generate the required system clock signals, ARMCLK for CPU, HCLK
for AXI/AHB-bus peripherals, and PCLK for the APB bus peripherals. There are three PLL’s in S3C6400. One is
for ARMCLK only. The second is for HCLK and PCLK. The third PLL is for peripheral, especially for audio related
clocks. The clock control logic can generate slow-rate clock-signals for ARMCLK, HCLK and PCLK by bypassing
externally supplied clock sources. The clock signal to each peripheral block can be enabled or disabled by
software control for the reduction of the power consumption.
In the power control logic, S3C6400 has various power management schemes to keep optimal power
consumption for a given task. The power management in S3C6400 consists of four modes: NORMAL (Clock
Gating and power gating), IDLE, STOP, DEEP-STOP and SLEEP.
General Clock Gating mode is used to control the ON/OFF of clocks for internal peripherals in S3C6400. The user
can optimize the power consumption of S3C6400 using this General Clock Gating mode by supplying clocks for
peripherals that are necessary for a certain application. For example, if a timer is not required the user can
disconnect the clock to the timer to reduce power.
IDLE mode disconnects the ARMCLK only to CPU core while it supplies the clock to all peripherals. By using
IDLE mode, the power consumption due to CPU core can be reduced.
STOP mode freezes all clocks to the CPU as well as peripherals by disabling PLL’s. The power consumption is
only due to the leakage current in S3C6400.
SLEEP mode is intended to disconnect the internal power. Therefore, the power consumption due to CPU and the
internal logic except the wakeup logic will be zero in the SLEEP mode. In order to use the SLEEP mode two
independent power sources are needed. One of the two power sources supplies the power for the wake-up logic.
The other one supplies the other internal logic including CPU, and should be controlled in order to be turned
ON/OFF. In SLEEP mode, the second power supply source for the CPU and internal logic will be turned off.
A detailed description of the power-saving modes such as the entering sequence to the specific power-down
mode or the wake-up sequence from a power-down mode are described in the Power Management section.
FEATURES
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Include three PLL’s: ARM PLL, main PLL, extra PLL (for the modules those use special frequency)
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Five power-saving mode: NORMAL, IDLE, STOP, DEEP-STOP, and SLEEP
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Five controllable power domain: domain-V, domain-I, domain-P, domain-F, domain-S
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Control operating clocks of internal sub-blocks