PRELIMINARY
S3C6400X RISC MICROPROCESSOR
IRDA
38
-17
Preliminary product information describe products that are in development,
for which full characterization data and associated errata are not yet available.
Specifications and information herein are subject to change without notice.
IRDA FIFO CONTROL REGISTER(IRDA_FCR)
Register
Address
R/W
Description
Reset Value
IrDA _FCR 0x7F00_7018
R/W
IrDA FIFO Control Register
0x00
IrDA _FCR
Bit
Description
Initial State
Rx FIFO Trigger level
select
[7:6]
Receiver FIFO triggers level selection.
Bit 7
Bit 6
64-byte RX FIFO
0 0
01
0 1
16
1 0
32
1 1
56
00
FIFO size select
[5]
Must set to ‘1’, to use 64 bytes TX and RX FIFO.
0
TX FIFO Clear
Notification
[4]
This bit will be activated when the FIFO clear is over. This
bit is cleared by the CPU reads this register.
0
RX FIFO CLEAR
NOTIFICATION
[3]
This bit will be activated when the FIFO clear is over. This
bit is cleared by the CPU reads this register.
0
Tx FIFO reset
[2]
TX FIFO reset. When set to ‘1’, bit 2 clears all bytes in the
transmitter FIFO and reset its counter to ‘0’. A ‘1’ written to
bit 2 is self-clearing.
0
Rx FIFO reset
[1]
RX FIFO reset. When set to ‘1’, bit 1 clears all bytes in the
receiver FIFO and reset its counter to ‘0’. A ‘1’ written to
bit 1 is self clearing.
0
FIFO enable
[0]
FIFO enabled. When set to ‘1’, bit 0 enables both the
transmitter and receiver FIFOs. Bit 0 must be a ‘1’ when
setting other IrDA_FCR bits. Changing bit 0 clears the
FIFO.
0