PRELIMINARY
DMA
S3C6400 RISC MICROPROCESSOR
11-20
Preliminary product information describe products that are in development,
for which full characterization data and associated errata are not yet available.
Specifications and information herein are subject to change without notice.
Configuration register, DMACConfiguration
The DMACConfiguration read/write register is used to configure the operation of the DMA controller. The
endianness of the individual AHB master interfaces can be altered by writing to the M1 and M2 bits of this register.
The M1 bit allows the endianness of AHB master interface 1 to be altered. The M2 bit allows the endianness of AHB
master interface 2 to be altered. The AHB master interfaces are set to little-endian mode on reset.
Table 11-14 shows the bit assignment of the DMACConfiguration register.
Table 11-14. Bit Assignment of DMACConfiguration register
DMACConfiguration
Bits
Type
Function
M2 [2]
R/W
AHB Master 2 endianness configuration:
0 =little-endian mode
1 =big-endian mode.
This bit is reset to 0.
M1 [1]
R/W
AHB Master 1 endianness configuration:
0 =little-endian mode
1 =big-endian mode.
This bit is reset to 0.
E [0]
R/W
DMA controller enable:
0 =disabled
1 =enabled.
This bit is reset to 0.Disabling the DMA controller reduces power
consumption.
Note:
It is not mandatory for AHB master interfaces to have the same endianness.
Synchronization register, DMACSync
The DMACSync read/write register is used to enable or disable synchronization logic for the DMA request signals.
The DMA request signals consist of the
DMACBREQ[15:0]
,
DMACSREQ[15:0]
,
DMACLBREQ[15:0]
, and
DMACLSREQ[15:0]
signals. A bit set to 0 enables the synchronization logic for a particular group of DMA requests.
A bit set to 1 disables the synchronization logic for a particular group of DMA requests.
This register is reset to 0, synchronization logic enabled.
Table 11-15 shows the bit assignment of the DMACSync register.
Table 11-15. Bit Assignment of DMACSync register
DMACSync
Bits
Type
Function
DMACSync [15:0]
R/W
DMA synchronization logic for DMA request signals enabled or disabled. A LOW
bit indicates that the synchronization logic for the
DMACBREQ[15:0]
,
DMACSREQ[15:0]
,
DMACLBREQ[15:0]
, and
DMACLSREQ[15:0]
request
signals is enabled. A HIGH bit indicates that the synchronization logic is disabled.
Note:
Synchronization logic must be used when the peripheral generating the DMA request runs on a different clock
to the DMA controller. For peripherals running on the same clock as the DMA controller disabling the