PRELIMINARY
DISPLAY CONTROLLER
S3C6400X RISC MICROPROCESSOR
14-46
Preliminary product information describe products that are in development,
for which full characterization data and associated errata are not yet available.
Specifications and information herein are subject to change without notice.
1 = Per pixel blending
BPPMODE_F
[5:2]
Select the BPP (Bits Per Pixel) mode Window image.
0000 = 1 BPP (LUT )
0001 = 2 BPP (LUT )
0010 = 4 BPP (LUT )
0011 = reserved
0100 = reserved
0101 = 16 BPP ( non-palletized, R:5-G:6-B:5 )
0110 = 16 BPP ( non-palletized, A:1-R:5-G:5-B:5 )
0111 = 16 BPP ( non-palletized, I :1-R:5-G:5-B:5 )
1000 = unpacked 18 BPP ( non-palletized, R:6-G:6-B:6 )
1001 = unpacked 18 BPP ( non-palletized, A:1-R:6-G:6-B:5 )
1010 = unpacked 19 BPP ( non-palletized, A:1-R:6-G:6-B:6 )
1011 = unpacked 24 BPP ( non-palletized R:8-G:8-B:8 )
1100 = unpacked 24 BPP ( non-palletized A:1-R:8-G:8-B:7 )
1101 = unpacked 25 BPP ( non-palletized A:1-R:8-G:8-B:8 )
111x = reserved
Note. 1101 can support unpacked 28 BPP also ( non-palletized
A:4-R:8-G:8-B:8 ) ,at BLD_PIX = 1.
0
ALPHA_SEL
[1]
Select Alpha value by
When ( BLD_PIX ==0)
0 = using ALPHA0_R/G/B values
1 = using ALPHA1_R/G/B values
When ( BLD_PIX ==1)
0 = selected by AEN (A value) or chroma key
1 = using DATA[27:24] data (only when BPPMODE_F = 4’b1101)
0
ENWIN_F
[0]
Video output and the logic immediately enable/disable.
0 = Disable the video output and the VIDEO control signal.
1 = Enable the video output and the VIDEO control signal.
0
Window 4 Control Register
Register
Address
R/W
Description
Reset Value
WINCON4 0x77100030
R/W Window
control 4 register
0x0000_0000
WINCON4
Bit
Description
Initial State
BITSWP
[18]
Bit swap control bit.
0 = Swap Disable 1 = Swap Enable
0