PRELIMINARY
S3C6400X RISC MICROPROCESSOR
USB2.0 HS OTG
26-41
Preliminary product information describe products that are in development,
for which full characterization data and associated errata are not yet available.
Specifications and information herein are subject to change without notice.
application sets the Port Reset bit or Port Resume
bit in this register or the Resume/Remote Wakeup
Detected Interrupt bit or Disconnect Detected
Interrupt bit in the Core Interrupt register.
·
1’b0 : Port not in Suspend mode
·
1’b1 : Port in Suspend mode
PrtRes [6]
R_W_
SS_SC
Port Resume
The application sets this bit to drive resume signaling
on the port. The core continues to drive the resume
signal until the application clears this bit. If the core
detects a USB remote wakeup sequence, as
indicated by the Port Resume/Remote Wakeup
Detected Interrupt bit of the Core Interrupt register,
the core starts driving resume signaling without
application intervention and clears this bit when it
detects a disconnect condition. The read value of
this bit indicates whether the core is currently driving
resume signaling.
·
1’b0 : No resume driven
·
1’b1 : Resume driven
1’b0
PrtOvrCurrChng [5]
R_SS_
WC
Port Overcurrent Change
The core sets this bit when the status of the Port
Overcurrent Active bit (bit 4) in this register changes.
1’b0
PrtOvrCurrAct
[4]
RO
Port Overcurrent Active
Indicates the overcurrent condition of the port.
·
1’b0 : No overcurrent condition
· 1’b1 : Overcurrent condition
1’b0
PrtEnChng [3]
R_SS_
WC
Port Enable/Disable Change
The core sets this bit when the status of the Port
Enable bit [2] of this register changes.
1’b0
PrtEna [2]
R_SS_
SC_WC
Port Enable
A port is enabled only by the core after a reset
sequence, and is disabled by an overcurrent
condition, a disconnect condition, or by the
application clearing this bit. The application cannot
set this bit by a register write. It can only clear it to
disable the port. This bit does not trigger any
interrupt to the application.
·
1’b0 : Port disabled
· 1’b1 : Port enabled
1’b0
PrtConnDet [1]
R_SS_
WC
Port Connect Detected
The core sets this bit when a device connection is
detected to trigger an interrupt to the application
using the Host Port Interrupt bit of the Core Interrupt
register. The application must write a 1 to this bit to
clear the interrupt.
1’b0
PrtConnSts
[0]
RO
Port Connect Status
·
1’b0 : No device is attached to the port
· 1’b1 : A device is attached to the port
1’b0