PRELIMINARY
S3C6400X RISC MICROPROCESSOR
SYSTEM CONTROLLER
3-35
Preliminary product information describe products that are in development,
for which full characterization data and associated errata are not yet available.
Specifications and information herein are subject to change without notice.
AHB_CON1 controls AHB-T0, AHB-T1, AHB-M0, AHB-M1 bus systems.
AHB_CON1
BIT
DESCRIPTION
RESET VALUE
DISABLE_HLOCK_M
[31]
Control HLOCK for M-block (0: disable, 1:enable)
0
RESERVED [30]
RESERVED
0
PRIOR_TYPE_M1
[29:28] Arbitration type for AHB-M1
0
RESERVED [27]
RESERVED
0
FIX_PRIOR_M1 [26:24]
Fixed
priority order for AHB-M1
0x0
RESERVED [23:22]
RESERVED
0x0
PRIOR_TYPE_M0
[21:20] Arbitration type for AHB-M0
0
RESERVED [19]
RESERVED
0
FIX_PRIOR_M0 [18:16]
Fixed
priority order for AHB-M0
0x0
DISABLE_HLOCK_T
[15]
Control HLOCK for T-block (0: disable, 1:enable)
0
RESERVED [14]
RESERVED
0
PRIOR_TYPE_T1
[13:12] Arbitration type for AHB-T1
0
RESERVED [11]
RESERVED
0
FIX_PRIOR_T1 [10:8]
Fixed
priority order for AHB-T1
0x0
RESERVED [7:6]
RESERVED 0x0
PRIOR_TYPE_T0
[5:4]
Arbitration type for AHB-T0
0
RESERVED [3]
RESERVED
0
FIX_PRIOR_T0 [2:0]
Fixed
priority order for AHB-T0
0x0
The arbitration numbers of the above bus system are as follows:
Arbitration Number
AHB-T0
AHB-T1
AHB-M0
AHB-M1
0
HOST I/F
HOST I/F
DMA0
DMA0
1 USB
Host - DMA1 DMA1
2 MDP
I/F -
-
-
3 - - - -
4 - - - -
5 - - - -
6 - - - -
7
Default bus master