Samsung S3C6400X, User Manual, Page: 348 / 1189

PRELIMINARY
S3C6400X RISC MICROPROCESSOR SECURITY SUB-SYSTEM
13-11
Preliminary product information describe products that are in development,
for which full characterization data and associated errata are not yet available.
Specifications and information herein are subject to change without notice.
FIFO-RX MESSAGE LENGTH COUNTER
Register Address R/W Description Reset Value
FRx_MLenCnt 0x7D40_0010 R/W FIFO-Rx Message Count Reg. (Number of words left) 0x0000_0000
FRx_MLenCnt Bit Description Initial State
FRx_MLenCnt [31:0] Number of words left for transfer. 0x0000_0000
FIFO-RX WRITE BUFFER
Register Address R/W Description Reset Value
0x7D40_0040
~
0x7D40_007C
FIFO-Rx write buffer (32-word)
Note: This address is for CPU access.
FRx_WrBuf
0x7D90_0040
~
0x7D90_007C
W
FIFO-Rx write buffer (32-word)
Note: This address is for SDMA1(Security DMA 1).
You should use it to transfer from memory to
FRx_WrBuf using SDMA1.
0x0000_0000
FRx_WrBuf Bit Description Initial State
FRx_WrBuf
[31:0]
FIFO-Rx write buffer (32x32-bit) 0x0000_0000
* Note: Write access to
FRx_WrBuf
makes FIFO-Rx to write data to the FIFO memory regardless of the address
given. That is, any address between 0x0040 and 0x007C will trigger the FIFO memory write. This feature lets
the programmer use burst write to the FIFO-Rx.