PRELIMINARY
S3C6400X RISC MICROPROCESSOR
MIPI HSI
28-15
Preliminary product information describe products that are in development,
for which full characterization data and associated errata are not yet available.
Specifications and information herein are subject to change without notice.
Address = BA 0x04 (0x7E00_6004)
Bits
Name
Description
R/W
Reset Value
[31:24] TxHOLD time
TxHOLD state timer setting value
R/W
0xFF
[23:16] TxIDLE time
TxIDLE state timer setting value
R/W
0xFF
[15:8]
TxREQ time
TxREQ state timer setting value
R/W
0xFF
[7] TxHOLD
time_en
TxHOLD state timer enabler
0 : disable 1 : enable
R/W 0x0
[6]
TxIDLE time_en
TxIDLE state timer enabler
0 : disable 1 : enable
R/W 0x0
[5]
TxREQ time_en
TxREQ state timer enabler
0 : disable 1 : enable
R/W 0x0
[4]
Err_clr
Generated Error clear
0 : stay 1 : clear
R/W 0x0
[3:2]
Width of CHID
Width of channel ID
R/W
0x0
[1]
Burst_mode
Fixed channel ID mode
0 : Burst ch ID mode 1 : Single ch ID mode
R/W 0x1
[0] Frame_mode
Frame
mode
0 : Stream mode 1 : Frame mode
R/W 0x0
Table 28-7 CONFIG_REG register description
INTSRC_REG
INTSRC_REG is interrupt source pending register.
Address = BA 0x0C (0x7E00_600C)
Bits
Name
Description
R/W
Reset Value
[31:5] Reserved
Reserved bits
R
0x000000
1
[4]
TxH_timeout
TxHOLD state timeout interrupt (set ‘1’ for clearing) R/W
0x0
[3]
TxI_timeout
TxIDLE state timeout interrupt (set ‘1’ for clearing)
R/W
0x0
[2]
TxR_timeout
TxREQ state timeout interrupt (set ‘1’ for clearing)
R/W
0x0