PRELIMINARY
DISPLAY CONTROLLER
S3C6400X RISC MICROPROCESSOR
14-48
Preliminary product information describe products that are in development,
for which full characterization data and associated errata are not yet available.
Specifications and information herein are subject to change without notice.
ENWIN_F
[0]
Video output and the logic immediately enable/disable.
0 = Disable the video output and the VIDEO control signal.
1 = Enable the video output and the VIDEO control signal.
0
Window 0 Position Control A Register
Register
Address
R/W
Description
Reset
Value
VIDOSD0A
0x77100040 R/W
Video Window 0’s position control register
0x0
VIDOSD0A
Bit
Description
initial
state
OSD_LeftTopX_F [21:11] Horizontal
screen
coordinate for left top pixel of OSD image
0
OSD_LeftTopY_F
[10:0]
Vertical screen coordinate for left top pixel of OSD image
(for interlace TV output, this value MUST be set to half of the
original screen y coordinate. And the original screen y coordinate
MUST be even value.)
0
Window 0 Position Control B Register
Register
Address
R/W
Description
Reset
Value
VIDOSD0B
0x77100044 R/W
Video Window 0’s position control register
0x0
VIDOSD0B
Bit
Description
initial
state
OSD_RightBotX_F [21:11] Horizontal screen coordinate for right bottom pixel of OSD image
0
OSD_RightBotY_F
[10:0]
Vertical screen coordinate for right bottom pixel of OSD image
(for interlace TV output, this value MUST be set to half of the
original screen y coordinate. And the original screen y coordinate
MUST be odd value.)
0
Note.
Registers must have word boundary X position.
So, 24 BPP mode must have X position by 1 pixel. ( ex, X = 0,1,2,3….)
16 BPP mode must have X position by 2 pixel. ( ex, X = 0,2,4,6….)
8 BPP mode must have X position by 4 pixel. ( ex, X = 0,4,8,12….)
Window 0 Position Control C Register
Register
Address
R/W
Description
Reset
Value
VIDOSD0C
0x77100048
R/W
Video Window 0’s Size control register
0x0