Samsung S3C6400X, User Manual, Page: 776 / 1189

PRELIMINARY
S3C6400X RISC MICROPROCESSOR MODEM INTERFACE
23-11
Preliminary product information describe products that are in development,
for which full characterization data and associated errata are not yet available.
Specifications and information herein are subject to change without notice.
Modem Interface Control Register (MIFCON)
Register Address R/W Description Reset Value
MIFCON 0x74108008 R/W Modem Interface Control register 0x00000008
MIFCON Bit Description Initial
State
Reserved [31:4]
- 0
INT2MSMEN [3]
Interrupt to MSM(Modem) Enable
: MSM_nIRQ is interrupt signal enable.
‘0’=Disable, ‘1’=Enable 1
INT2APEN [2]
MSM(Modem) write interrupt to AP Enable
‘0’=Disable, ‘1’=Enable 0
Reserved [1]
Reserved 0
Fixed [0]
Fixed to 0 0
Modem Interface Port Control Register (MIFPCON)
Register Address R/W Description Reset Value
MIFPCON 0x7410800C R/W Modem Interface Port Control register 0x00000008
MIFCON Bit Description Initial
State
Reserved [31:6]
- 0
Reserved [5]
Fixed to 0 0
INT2M_LEVEL [4]
Interrupt to MSM(Modem) Active High
: MSM_nIRQ interrupt signal make active high when this bit is set
to High.
‘0’=Disable, ‘1’=Enable
Note : “INV_INTR” field of the HOST I/F block and
“INT2M_LEVEL” of the MODEM I/F block should have same
polarity. 0
SEL_BYPASS [3]
Select (mux) control for LCD bypass ( from Modem/Host Interface
to LCD i80 interface)
‘0’ = Normal mode
‘1’ = Bypass mode (initial value) 1
SEL_RS [2:0]
RS selection for LCD Bypass path
3’b000 : XhiADDR[8] -> bypass_RS
3’b001 : XhiADDR[7] -> bypass_RS
3’b010 : XhiADDR[6] -> bypass_RS
3’b011 : XhiADDR[5] -> bypass_RS
3’b100 : XhiADDR[4] -> bypass_RS
3’b101 : XhiADDR[3] -> bypass_RS 0