PRELIMINARY
S3C6400X RISC MICROPROCESSOR
DISPLAY
CONTROLLER
14-57
Preliminary product information describe products that are in development,
for which full characterization data and associated errata are not yet available.
Specifications and information herein are subject to change without notice.
00 = None 01 = BACK Porch
10 = VSYNC 11 = FRONT Porch
INTFRMEN
[12]
Video Frame interrupts Enable control bit.
0 = Video Frame Interrupt Disable
1 = Video Frame Interrupt Enable
0
FIFOSEL
[11:5]
FIFO Interrupt control bit, each bit has the meaning of
[11] Window 4 control ( 0: disable, 1: enable)
[10] Window 3 control ( 0: disable, 1: enable)
[ 9] Window 2 control ( 0: disable, 1: enable)
[ 8] reserved
[ 7] reserved
[ 6] Window 1 control ( 0: disable, 1: enable)
[ 5] Window 0 control ( 0: disable, 1: enable)
0
FIFOLEVEL
[4:2]
Video FIFO Interrupt Level Select
000 = 0 ~ 25%
001 = 0 ~ 50%
010 = 0 ~ 75%
011 = 0% (empty)
100 = 100% (full)
0
INTFIFOEN
[1]
Video FIFO interrupts Enable control bit.
0 = Video FIFO Level Interrupt Disable
1 = Video FIFO Level Interrupt Enable
0
INTEN
[0]
Video interrupts Enable control bit.
0 = Video Interrupt Disable
1 = Video Interrupt Enable
0
VIDEO interrupt Control 1 Register
Register
Address
R/W
Description
Reset Value
VIDINTCON1
0x77100134
R/W
the Video interrupt Pending register
0x00000000
VIDINTCON1
Bit
Description
Initial
state
- [4:3]
Reserved
0
INTI80PEND
[2]
I80 Done interrupt. To clear this bit, write “1” .
0 = The interrupt has not been requested
1 = I80 Done status has asserted the interrupt request
0
INTFRMPEND
[1]
Frame sync interrupt. To clear this bit, write “1” .
0 = The interrupt has not been requested
1 = Frame sync status has asserted the interrupt request
0