PRELIMINARY
S3C6400X RISC MICROPROCESSOR VECTORED INTERRUPT CONTROLLER
12-9
Preliminary product information describe products that are in development,
for which full characterization data and associated errata are not yet available.
Specifications and information herein are subject to change without notice.
REGISTER DESCRIPTIONS
IRQ Status Register, VICIRQSTATUS
Bits
Name
Type
Function
[31:0]
IRQStatus
R
Show the status of the interrupts after masking by the
VICINTENABLE and VICINTSELECT Registers:
0 = interrupt is inactive (reset)
1 = interrupt is active.
There is one bit of the register for each interrupt source.
FIQ Status Register, VICFIQSTATUS
Bits
Name
Type
Function
[31:0]
FIQStatus
R
Show the status of the FIQ interrupts after masking by
the VICINTENABLE and VICINTSELECT Registers:
0 = interrupt is inactive (reset)
1 = interrupt is active.
There is one bit of the register for each interrupt source.
Raw Interrupt Status Register, VICRAWINTR
Bits
Name
Type
Function
[31:0] RawInterrupt R
Show the status of the FIQ interrupts before masking by
the VICINTENABLE and VICINTSELECT Registers:
0 = interrupt is inactive before masking
1 = interrupt is active before masking
Because this register provides a direct view of the raw
interrupt inputs, the reset value is unknown.
There is one bit of the register for each interrupt source.
Interrupt Select Register, VICINTSELECT
Bits
Name
Type
Function
[31:0] IntSelect RW
Selects type of interrupt for interrupt request:
0 = IRQ interrupt (reset)