Samsung S3C6400X, User Manual, Page: 340 / 1189

PRELIMINARY
S3C6400X RISC MICROPROCESSOR SECURITY SUB-SYSTEM
13-3
Preliminary product information describe products that are in development,
for which full characterization data and associated errata are not yet available.
Specifications and information herein are subject to change without notice.
SPECIAL FUNCTION REGISTERS
Security Sub-system Register Map
Table 1 DMA & Interrupt Control Register Map
Address R/W Reset value Name Description
Base + 0x00 R/W 0x0000_0000 DnI_CFG DMA and interrupt configuration register
* Base = 0x7D00_0000
Table 2 FIFO-Rx Register Map
Address R/W Reset value Name Description
Base + 0x00 R/W 0x0420_0000 FRx _Ctrl FIFO-Rx Control & Status register
Base + 0x04 R/W 0x0000_0000 FRx _MLen FIFO-Rx Message Length register
Base + 0x08 R/W 0x0000_0000 FRx _BlkSz FIFO-Rx Crypto algorithm block size register
Base + 0x0C R/W 0x0000_0000 FRx _DestAddr FIFO-Rx Inout Buffer Address register
Base + 0x10 R/W 0x0000_0000 FRx _MLenCnt FIFO-Rx Message Count register
Base + 0x40 W 0x0000_0000 FRx _WrBuf FIFO-Rx write buffer
… … … … …
Base + 0x7C W
0x0000_
0000 FRx _WrBuf FIFO-Rx write buffer
* Base = 0x7D40_0000
* Base=0x7D90_0000 (Have to use this address to transfer using SDMA1, SDMA1 only see this address. )
* Note: Write access to
FRx_WrBuf
makes FIFO-Rx to write data to the FIFO memory regardless of the address
given. That is, any address between 0x0040 and 0x007C will trigger the FIFO memory write. This feature lets the
programmer use burst write to the FIFO-Rx.
Table 3 FIFO-Tx Register Map
Address R/W Reset value Name Description
Base + 0x00 R/W 0x0420_0000 FTx _Ctrl FIFO-Tx Control & Status register
Base + 0x04 R/W 0x0000_0000 FTx _MLen FIFO-Tx Message Length register
Base + 0x08 R/W 0x0000_0000 FTx _BlkSz FIFO-Tx Crypto algorithm block size register
Base + 0x0C R/W 0x0000_0000 FTx _DestAddr FIFO-Tx Inout Buffer Address register
Base + 0x10 R/W 0x0000_0000 FTx _MLenCnt FIFO-Tx Message Count register
Base + 0x40 R 0x0000_0000 FTx _RdBuf FIFO-Tx read buffer
… … … … …
Base + 0x7C R
0x0000_
0000 FTx _RdBuf FIFO-Tx read buffer
* Base = 0x7D80_0000
* Base=0x7DA0_0000 (Have to use this address to transfer using SDMA1, SDMA1 only see this address. )
z
Note: Read access to
FTx_WrBuf
makes FIFO-Tx to read data from the FIFO memory regardless of the
address given. That is, any address between 0x0040 and 0x0080 will trigger the FIFO memory read. This
feature makes the programmer use burst read to the FIFO-Tx.