PRELIMINARY
S3C6400X RISC MICROPROCESSOR
MULTI-FORMAT VIDEO CODEC
21-68
Preliminary product information describe products that are in development,
for which full characterization data and associated errata are not yet available.
Specifications and information herein are subject to change without notice.
3’b100 (SET_FRAME_BUF): Set decoded/
reconstructed frame buffer SDRAM address and
maximum frame buffer number. Before
encode/decode picture run command, host must
inform frame buffer SDRAM address to BIT
processor then BIT processor arrange frame buffer
for decoded/reconstructed image and return frame
buffer index to host at end of encoding/decoding
picture.
3’b101 (ENCODE HEADER): Encode header. For
example in H.264 case, SPS (Sequence Parameter
Set), PPS (Picture Parameter Set) may be inserted
between picture boundary by this command.
3’b110 (ENC PARA SET): Encode SPS, PPS to BIT
processor’s parameter set buffer. In H.264, host can
obtain SPS / PPS by this command
3’b111 (DEC PARA SET): Add SPS, PPS to BIT
processor’s parameter set buffer. In H.264, multiple
SPS / PPS is allowed and host may inform one of
the parameter set to BIT processor for use in
decoding process.
4’b1111 (GET F/W VER): A command to check F/W
version. This command is only applicable to F/W
version later than 1.2.5.
RunIndex (0x168)
Bit
Name
Type
Function
Reset
Value
1:0 RunIndex R/W
Host
writes the codec process index to this register
before every writing run command.
BIT processor can execute max 4 encoding/decoding
processes simultaneously. If more than one process is
running, each process must be assigned different
process index by this register. For example, when 1
MPEG4 D 1 AVC D 1 AVC Encoder
are running simultaneously, MPEG4 Decoder is
assigned process index ‘0’, AVC Decoder is assigned
process index ‘1’ and AVC Encoder is assigned
process index ‘2’.
N/A