Samsung S3C6400X, User Manual, Page: 64 / 1189

PRELIMINARY
S3C6400X RISC MICROPROCESSOR SYSTEM CONTROLLER
3-19
Preliminary product information describe products that are in development,
for which full characterization data and associated errata are not yet available.
Specifications and information herein are subject to change without notice.
REGISTER DESCRIPTION
System controller controls PLL, clock generator, the power management part, and other system dependent part.
This section describe how to control these part using SFR(Special Functional Register) within the system
controller.
MEMORY MAP
The followings show 34 registers within system controller.
Register Address R/W Description Reset Value
APLL_LOCK 0x7E00_F000 R/W Control PLL locking period for APLL 0x0000_FFFF
MPLL_LOCK 0x7E00_F004 R/W Control PLL locking period for MPLL 0x0000_FFFF
EPLL_LOCK 0x7E00_F008 R/W Control PLL locking period for EPLL 0x0000_FFFF
APLL_CON 0x7E00_F00C R/W Control PLL output frequency for APLL 0x0190_0302
MPLL_CON 0x7E00_F010 R/W Control PLL output frequency for MPLL 0x0214_0603
EPLL_CON0 0x7E00_F014 R/W Control PLL output frequency for EPLL 0x0020_0102
EPLL_CON1 0x7E00_F018 R/W Control PLL output frequency for EPLL 0x0000_9111
CLK_SRC 0x7E00_F01C R/W Select clock source 0x0000_0000
CLK_DIV0 0x7E00_F020 R/W Set clock divider ratio 0x0105_1000
CLK_DIV1 0x7E00_F024 R/W Set clock divider ratio 0x0000_0000
CLK_DIV2 0x7E00_F028 R/W Set clock divider ratio 0x0000_0000
CLK_OUT 0x7E00_F02C R/W Select clock output 0x0000_0000
HCLK_GATE 0x7E00_F030 R/W Control HCLK clock gating 0xFFFF_FFFF
PCLK_GATE 0x7E00_F034 R/W Control PCLK clock gating 0xFFFF_FFFF
SCLK_GATE 0x7E00_F038 R/W Control SCLK clock gating 0xFFFF_FFFF
RESERVED
0x7E00_F03C~
0x7E00_F0FC
- RESERVED -
AHB_CON0 0x7E00_F100 R/W Configure AHB I/P/X/F bus 0x0400_0000
AHB_CON1 0x7E00_F104 R/W Configure AHB M1/M0/T1/T0 bus 0x0000_0000
AHB_CON2 0x7E00_F108 R/W Configure AHB R/S1/S0 bus 0x0000_0000
RESERVED 0x7E00_F10C - RESERVED -
SDMA_SEL 0x7E00_F110 R/W Select secure DMA input 0x0000_0000
SW_RST 0x7E00_F114 R/W Generate software reset 0x0000_0000
SYS_ID 0x7E00_F118 R System ID for revision and pass 0x0000_0000
RESERVED 0x7E00_F11C - RESERVED -
MEM_SYS_CFG 0x7E00_F120 R/W Configure memory subsystem 0x0000_0080
QOS_OVERRIDE0 0x7E00_F124 R/W Override DMC0 QOS 0x0000_0000
QOS_OVERRIDE1 0x7E00_F128 R/W Override DMC1 QOS 0x0000_0000