Samsung S3C6400X, User Manual, Page: 129 / 1189

PRELIMINARY
S3C6400X RISC MICROPROCESSOR SROM CONTROLLER
6-7
Preliminary product information describe products that are in development,
for which full characterization data and associated errata are not yet available.
Specifications and information herein are subject to change without notice.
SROM BANK CONTROL REGISTER (SROM_BC : XrCSn0 ~ XrCSn2)
Register Address R/W Description Reset Value
SROM_BC0
0x70000004 R/W SROM Bank0 control register 0x000F_0000
SROM_BC1
0x70000008 R/W SROM Bank1 control register 0x000F_0000
SROM_BC2
0x7000000C R/W SROM Bank2 control register 0x000F_0000
SROM_BC3
0x70000010 R/W SROM Bank3 control register 0x000F_0000
SROM_BC4
0x70000014 R/W SROM Bank4 control register 0x000F_0000
SROM_BC5
0x70000018 R/W SROM Bank5 control register 0x000F_0000
SROM_BCn Bit Description Initial State
Tacs
[31:28] Adress set-up before nGCS
0000 = 0 clock
0001 = 1 clocks
0010 = 2 clocks 0011 = 3 clocks
………….
1100 = 12 clocks 1101 = 13 clocks
1110 = 14 clocks 1111 = 15 clocks
0000
Tcos [27:24] Chip selection set-up before nOE
0000 = 0 clock
0001 = 1 clocks
0010 = 2 clocks 0011 = 3 clocks
………….
1100 = 12 clocks 1101 = 13 clocks
1110 = 14 clocks 1111 = 15 clocks
0000
Reserved [23:21] Reserved 000
Tacc
[20:16] Access cycle
00000 = 1 clock 00001 = 2 clocks
00010 = 3 clocks 0001 1 = 4 clocks
………….
11100 = 29 clocks 11101 = 30 clocks
11110 = 31 clocks 11111 = 32 clocks
01111
Tcoh [15:12] Chip selection hold on nOE
0000 = 0 clock
0001 = 1 clocks
0010 = 2 clocks 0011 = 3 clocks
………….
1100 = 12 clocks 1101 = 13 clocks
1110 = 14 clocks 1111 = 15 clocks
0000
Tcah [11:8] Address holding time after nGCSn
0000 = 0 clock
0001 = 1 clocks
0010 = 2 clocks 0011 = 3 clocks
………….
1100 = 12 clocks 1101 = 13 clocks
1110 = 14 clocks 1111 = 15 clocks
0000
Tacp
[7:4] Page mode access cycle @ Page mode
0000 = 0 clock
0001 = 1 clocks
0010 = 2 clocks 0011 = 3 clocks
………….
1100 = 12 clocks 1101 = 13 clocks
0000