Samsung S3C6400X, User Manual, Page: 837 / 1189

PRELIMINARY
USB2.0 HS OTG S3C6400X RISC MICROPROCESSOR
26-30
Preliminary product information describe products that are in development,
for which full characterization data and associated errata are not yet available.
Specifications and information herein are subject to change without notice.
ConIDStsChngMsk [28] R_W Connector ID Status Change Mask 1’b0
[27] Reserved 1’b0
PTxFEmpMsk [26] R_W Periodic TxFIFO Empty Mask 1’b0
HChIntMsk [25] R_W Host Channels Interrupt Mask 1’b0
PrtIntMsk [24] R_W Host Port Interrupt Mask 1’b0
[23] Reserved 1’b0
FetSuspMsk [22] R_W Data Fetch Suspended Mask 1’b0
Incomplete Periodic Transfer Mask incomplPMsk
incompISOOUTMsk
[21] R_W
Incomplete Isochronous OUT Transfer Mask
1’b0
incompISOINMsk [20] R_W Incomplete Isochronous IN Transfer Mask 1’b0
OEPIntMsk [19] R_W OUT Endpoints Interrupt Mask 1’b0
INEPIntMsk [18] R_W IN Endpoints Interrupt Mask 1’b0
EPMisMsk [17] R_W Endpoint Mismatch Interrupt Mask 1’b0
[16] Reserved 1’b0
EOPFMsk [15] R_W End of Periodic Frame Interrupt Mask 1’b0
ISOOutDropMsk [14] R_W Isochronous OUT Packet Dropped Interrupt Mask 1’b0
EnumDoneMsk [13] R_W Enumeration Done Mask 1’b0
USBRstMsk [12] R_W USB Reset Mask 1’b0
USBSuspMsk [11] R_W USB Suspend Mask 1’b0
ErlySuspMsk [10] R_W Early Suspend Mask 1’b0
[9] Reserved 1’b0
[8] Reserved 1’b0
GOUTNakEffMsk [7] R_W Global OUT NAK Effective Mask 1’b0
GINNakEffMsk [6] R_W Global Non-Periodic IN NAK Effective Mask 1’b0
NPTxFEmpMsk [5] R_W Non-Periodic TxFIFO Empty Mask 1’b0
RxFLvlMsk [4] R_W Receive FIFO Non-Empty Mask 1’b0
SofMsk [3] R_W Start of (micro)Frame Mask 1’b0
OTGIntMsk [2] R_W OTG Interrupt Mask 1’b0
ModeMisMsk [1] R_W Mode Mismatch Interrupt Mask 1’b0
[0] Reserved 1’b0
RECEIVE STATUS DEBUG READ/STATUS READ AND POP REGISTERS (GRXSTSR/GRXSTSP)
A read to the Receive Status Debug Read register returns the contents of the top of the Receive FIFO. A read to
the Receive Status Read and Pop register additionally pops the top data entry out of the RxFIFO.
The receive status contents must be interpreted differently in Host and Device modes. The core ignores the