PRELIMINARY
S3C6400X RISC MICROPROCESSOR
MIPI HSI
28-23
Preliminary product information describe products that are in development,
for which full characterization data and associated errata are not yet available.
Specifications and information herein are subject to change without notice.
SWRST_REG
SWRST_REG is software reset.
Address = BA 0x14
Bits
Name
Description
R/W
Reset Value
[31:1] Reserved
Reserved bits
R
0x00000000
[0] Sw_rst
Software
reset
0 : set 1 : reset
R/W 0x0
Table 28-18 SWRST_REG register description
CHID_REG
CHID_REG is channel ID RxFIFO output.
Address = BA 0x18
Bits
Name
Description
R/W
Reset Value
[31:3] Reserved
Reserved bits
R
0x0000000
[2:0]
CURR_ID
Current Channel ID
R
0x0
Table 28-19 CHID_REG register description
Note:
Channel ID is read once when Data is written in FIFO again after FIFO become empty, because Data in Rx
Data FIFO have the same channel ID.
DATA_REG
DATA_REG is RxFIFO output.
Address = BA 0x1C
Bits
Name
Description
R/W
Reset Value
[31:0] RxFIFO
out
RxFIFO data output
R
0x0
Table 28-20 DATA_REG register description