PRELIMINARY
HSMMC CONTROLLER
S3C6400X RISC MICROPROCESSOR
27-62
Preliminary product information describe products that are in development,
for which full characterization data and associated errata are not yet available.
Specifications and information herein are subject to change without notice.
[15:14]
Reserved
0
[13:8]
Base Clock Frequency For SD Clock
(HWInit)
This value indicates the base (maximum) clock frequency for the SD
Clock. Unit values are 1MHz. If the real frequency is 16.5MHz, the lager
value is set to 01 0001b (17MHz) because the Host Driver use this value
to calculate the clock divider value (Refer to the
SDCLK Frequency
Select
in the
Clock Control
register.) and it does not exceed upper limit
of the SD Clock frequency. The supported clock range is 10MHz to
63MHz. If these bits are all 0, the Host System has to get information via
another method.
Not ‘0’=1MHz to 63MHz
000000b = Get information via another method
0
[7]
Timeout Clock Unit
(HWInit)
This bit shows the unit of base clock frequency used to detect
Data
Timeout Error
.
‘0’=KHz, ‘1’=MHz
1
[6]
Reserved
0
[5:0]
Timeout Clock Frequency
(HWInit)
This bit shows the base clock frequency used to detect
Data Timeout
Error
. The
Timeout Clock Unit
defines the unit of this field value.
Timeout Clock Unit
=0 [KHz] unit: 1KHz to 63KHz
Timeout Clock Unit
=1 [MHz] unit: 1MHz to 63MHz
Not 0 = 1KHz to 63KHz or 1MHz to 63MHz
00 0000b = Get information via another method
0