PRELIMINARY
S3C6400X RISC MICROPROCESSOR
MULTI-FORMAT VIDEO CODEC
21-2
Preliminary product information describe products that are in development,
for which full characterization data and associated errata are not yet available.
Specifications and information herein are subject to change without notice.
FIMV-MFC V1.0 video codec is optimized to reduce the logic gate count with sharing large parts of sub-
modules for multi-standard. Motion estimation module uses a search RAM to reduce the bandwidth on the
external SDRAM. Generally, motion estimation reads reference pixel data several times. The motion estimation
module loads the reference pixel data form the external SDRAM and store them into the search RAM. The search
RAM is accessed through the AMBA AHB.
The macroblock sequencer module schedules the processing flow of the functional blocks of the video codec to
reduce loads on the BIT processor and complexity of the firmware. FIMV-MFC V1.0 includes a rotation/mirroring
module. In case of rotating and/or mirroring the source image in the encoder, no additional bandwidth is required
for the processing. However, in the decoder, the decoded image with any rotation and/or mirroring is written to the
external memory.
The internal AXI arbiter module arbitrates requests from internal DMA controllers to ease the integration to user’s
SoC.
Figure 21.2 describes roles of the BIT processor, video codec core module and how to interface with
application software. Basically, at the frame level, a host processor communicates with FIMV-MFC V1.0 through
provided API’s. To give the video codec more flexibility and debugging capability, all processes related to the
bitstream are assigned to the BIT processor.
Figure 21.2. Roles of the BIT processor and the video codec module