PRELIMINARY
DRAM CONTROLLER
S3C6400X RISC MICROPROCESSOR
5-2
Preliminary product information describe products that are in development,
for which full characterization data and associated errata are not yet available.
Specifications and information herein are subject to change without notice.
z
Supports 2 outstanding exclusive access transfers.
z
Configurable memory access timing by using SFRs.
z
Support extended MRS (EMRS) set.
z
For Memory Port 1, CKE can be controlled separately.
z
For Memory Port 1, Not supports 16bit SDR SDRAM, mobile SDR SDRAM
BLOCK DIAGRAM
Following figure 5-1 shows the block diagram of PL340 DRAM Controller
AXI domain
APB domain
Memory
domain
APB
slave
interface
AMBA 3.0 APB
interface
Memory
interface
Pad
interface
External
memory
interface
to SDRAM
AXI
slave
interface
Arbiter
Memory
manager
AXI low-power
interface channel
Read address
channel
Write address
channel
Buffered write
response channel
Write
channel
Read
channel
Read data
Figure 5-1 DRAM Controller Block Diagram