Samsung S3C6400X, User Manual, Page: 115 / 1189

PRELIMINARY
S3C6400X RISC MICROPROCESSOR DRAM CONTROLLER
5-9
Preliminary product information describe products that are in development,
for which full characterization data and associated errata are not yet available.
Specifications and information herein are subject to change without notice.
Row bits [5:3]
Encodes the number of bits of the AXI address that comprise the
row address:
000 = 11 bits
001 = 12 bits
010 = 13 bits
011 = 14 bits
100 = 15 bits
101 = 16 bits
110 = 10 bits
111 = 9 bits
100
Column bits [2:0]
Encodes the number of bits of the AXI address that comprise the
column address:
000 = 8 bits
001 = 9 bits
010 = 10 bits
011 = 11 bits
100 = 12 bits
101 = 7 bits
110 = 6 bits
111 = Reserved.
000
REFRESH PERIOD REGISTER
Register Address R/W Description Reset Value
P0REFRESH 0x7E000010 R/W 16-bit DRAM controller refresh period register 0xA60
P1REFRESH 0x7E001010 R/W 32-bit DRAM controller refresh period register 0xA60
PnREFRESH Bit Description Initial State
[31:15] Read undefined. Write as Zero
Refresh perod [14:0] Memory refresh period in memory clock cycles. 0xA60
CAS LATENCY REGISTER
Register Address R/W Description Reset Value
P0CASLAT 0x7E000014 R/W 16-bit DRAM controller CAS latency register 0x6
P1CASLAT 0x7E001014 R/W 32-bit DRAM controller CAS latency register 0x6
PnCASLAT Bit Description Initial State
[31:4] Read undefined. Write as Zero
CAS Latency [3:1] CAS latency in memory clock cycles. 011