PRELIMINARY
SPI CONTROLLER
S3C6400X RISC MICROPROCESSOR
29-6
Preliminary product information describe products that are in development,
for which full characterization data and associated errata are not yet available.
Specifications and information herein are subject to change without notice.
TxChOn [0]
R/W
SPI Tx Channel On
0: Channel Off 1: Channel On
1’b0
Register
Address
R/W
Description
Reset Value
Clk_CFG(Ch0) 0x7F00B004 R/W Clock
configuration register
0x0
Clk_CFG(Ch1) 0x7F00C004 R/W Clock
configuration register
0x0
Clk_CFG
Bit
Description
Initial State
ClkSel [10:9]
R/W
Clock source selection to generate SPI clock-out
00 : PCLK 01 : USBCLK
10 : Epll clock 11 : reserved
*
For using USBCLK source, The USB_SIG_MASK at
system controller must be set to on.
2’b0
ENCLK [8]
R/W
Clock on/off
0 : disable 1 : enable
1’b0
Prescaler
Value
[7:0]
R/W
SPI clock-out division rate
SPI clock-out =
Clock source / ( 2 x (Prescaler value +1))
8’h0
Register
Address
R/W
Description
Reset Value
MODE_CFG(Ch0) 0x7F00B008 R/W SPI
FIFO control register
0x0
MODE_CFG(Ch1) 0x7F00C008 R/W SPI
FIFO control register
0x0
MODE_CFG
Bit
Description
Initial State
Ch_tran_size
[30:29]
R/W
00 : Byte 01 : Halfword
10 : word 11 : reserved
2’b0
Trailing Count
[28:19]
R/W
Count value from writing the last data in RX
FIFO to flush trailing bytes in FIFO
10’b0
BUS transfer size
[18:17]
R/W
00: byte 01: halfword
10 : word 11:reserved
2’b0
RxTrigger [16:11]
R/W
Rx FIFO trigger level in INT mode. Trigger
level is from 6’h0 to 6’h40. The value means
byte number in RX FIFO
6’b0
TxTrigger [10:5]
R/W
Tx FIFO trigger level in INT mode
Trigger level is from 6’h0 to 6’h40. The value
means byte number in TX FIFO
6’b0