Samsung S3C6400X, User Manual, Page: 599 / 1189

PRELIMINARY
CAMERA INTERFACE S3C6400X RISC MICROPROCESSOR
20-34
Preliminary product information describe products that are in development,
for which full characterization data and associated errata are not yet available.
Specifications and information herein are subject to change without notice.
CICOSTATUS Bit Description
Initial
State
M L
OvFiY_Co [31] Overflow state of codec FIFO Y 0
X X
OvFiCb_Co [30] Overflow state of codec FIFO Cb 0
X X
OvFiCr_Co [29] Overflow state of codec FIFO Cr 0
X X
VSYNC [28]
Camera VSYNC (This bit can be referred by CPU for first SFR
setting after external camera muxing. It can be seen in the ITU-R
BT 656 mode)
0
X X
FrameCnt_Co [27:26]
Frame count of codec DMA (This counter value means the next
frame number)
0
X X
WinOfstEn_Co [25] Window offset enable status 0
X X
FlipMd_Co [24:23] Flip mode of codec DMA 0
X X
ImgCptEn [22] Image capture enable of global camera interface 0
X X
ImgCptEn_CoSC [21] Image capture enable of codec path 0
X X
VSYNC_A [20] External camera A VSYNC (polarity inversion was not adopted.) X
X X
reserved [19] X
X X
reserved [18] X X X
FrameEnd_Co [17]
When codec frame operation finish, FrameEnd_Co is generated.
and FrameEnd_Co is clear by user setting ‘0’
0
X X
Reserved [16:0] 0
X X
PREVIEW OUTPUT Y1 START ADDRESS REGISTER
Register Address R/W Description Reset Value
CIPRYSA1 0x7800006C RW 1
st
frame start address for preview DMA
0
CIPRYSA1 Bit Description
Initial
State
M L
CIPRYSA1 [31:0] Non-Interleave Y, Interleave YCbCr, RGB : 1
st
frame start address 0
O X
PREVIEW OUTPUT Y2 START ADDRESS REGISTER
Register Address R/W Description Reset Value
CIPRYSA2 0x78000070 RW 2
nd
frame start address for preview DMA
0
CIPRYSA2 Bit Description
Initial
State
M L
CIPRYSA2 [31:0] Non-Interleave Y, Interleave YCbCr, RGB : 2
nd
frame start address 0
O X