ST10R272L - SYSTEM RESET
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256 words of system stack are available, where the system stack selected by the SP grows
downwards from 00’FBFEh, while the register bank selected by the CP grows upwards from
00’FC00h.
Based on the application, the user may wish to initialize portions of the internal memory
before normal program operation. Once the register bank has been selected by
programming the CP register, the desired portions of the internal memory can easily be
initialized via indirect addressing.
At the end of the initialization, the interrupt system may be globally enabled by setting bit IEN
in register PSW. Care must be taken not to enable the interrupt system before the
initialization is complete.
The software initialization routine should be terminated with the EINIT instruction. This
instruction has been implemented as a protected instruction. Execution of the EINIT
instruction disables the action of the DISWDT instruction, disables write accesses to register
SYSCON (see note) and causes the RSTOUT pin to go high. This signal can be used to
indicate the end of the initialization routine and the proper operation of the microcontroller to
external hardware.
Note
All configurations regarding register SYSCON (enable CLKOUT, stacksize, etc.)
must be selected before the execution of EINIT.
15.10.1 System start-up configuration
Although most of the programmable features of the ST10R272L are either selected during
the initialization phase or repeatedly during program execution, there are some features that
must be selected earlier, because they are used for the first access of the program execution
(e.g. external bus configuration).
These selections are made during reset via the pins of PORT0, which are read during the
internal reset sequence. During reset internal pullup devices are active on the PORT0 lines,
so their input level is high, if the respective pin is left open, or is low, if the respective pin is
connected to an external pulldown device. The coding of the selections, as shown below,
allows in many cases to use the default option, i.e. high level.
The value on the upper byte of PORT0 (P0H) is latched into register RP0H upon hardware
reset, the value on the lower byte (P0L) in conjunction with the value of EA pin directly
influences the SYSCON and BUSCON0 registers (bus mode) or the internal control logic of
the ST10R272L.
The pins that control the operation of the internal control logic (P0L.0, P0L.1) and the
reserved pins are evaluated only during a hardware triggered reset sequence. The pins that
influence the configuration of the ST10R272L (P0L.6, P0L.7 and P0H.0) are evaluated
during any reset sequence, i.e. also during software and watchdog timer triggered resets.
