ST10R272L - MULTIPLY-ACCUMULATE UNIT (MAC)
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5.3
MAC register set
5.3.1 Address
registers
The new addressing modes require new (E)SFRs: 2 address pointers IDX0 / IDX1 and 4
offset registers QX0 / QX1 and QR0 / QR1.
IDX0 (FF08h / 84h)
SFR
Reset Value: 0000h
IDX1 (FF0Ah / 85h)
SFR
Reset Value: 0000h
QX0 (F000h / 00h)
ESFR
Reset Value: 0000h
QX1 (F002h / 01h)
ESFR
Reset Value: 0000h
QR0 (F004h / 02h)
ESFR
Reset Value: 0000h
QR1 (F006h / 03h)
ESFR
Reset Value: 0000h
5.3.2
Accumulator & control registers
The MAC unit SFRs include the 40-bit Accumulator (MAL, MAH and the low byte of MSW)
and 3 control registers: the status word MSW, the control word MCW and the repeat word
MRW.
Bit
Function
IDXy
16-bit IDXy address
Bit
Function
QRz/QXz
16-bit address offset for IDXy pointers (QXz) or GPR pointers (QRz).
As MAC instructions handle word operands, bit 0 of these offset registers is hardwired to ‘0’.
5
4
3
2
1
0
11
10
9
8
7
6
15
14
13
12
rw
IDXy
5
4
3
2
1
0
11
10
9
8
7
6
15
14
13
12
rw
QXz/QRz
0
r
