ST10R272L - INTERRUPT AND TRAP FUNCTIONS
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instruction. When the SP is incremented by an add instruction, the IP value represents the
address of the instruction after the instruction following the add instruction.
6.9.7
Undefined opcode trap
When the instruction currently decoded by the CPU does not contain a valid ST10R272L
opcode, the UNDOPC flag is set in register TFR and the CPU enters the undefined opcode
trap routine. The IP value pushed onto the system stack is the address of the instruction that
caused the trap.
This can be used to emulate unimplemented instructions. The trap service routine can
examine the faulting instruction, to decode operands for non-implemented opcodes based
on the stacked IP. To resume processing, the stacked IP value must be incremented by the
size of the undefined instruction (determined by the user), before a RETI instruction is
executed.
6.9.8
Protection fault trap
When a protected instruction is executed without its opcode being repeated twice in the
second word of the instruction, and the byte following the opcode is not the complement of
the opcode, the PRTFLT flag in the TFR register is set and the CPU enters the protection
fault trap routine. The protected instructions include DISWDT, EINIT, IDLE, PWRDN, SRST,
and SRVWDT. The IP value pushed onto the system stack for the protection fault trap is the
address of the instruction that caused the trap.
6.9.9
Illegal word operand access trap
Whenever a word operand read or write access is attempted to an odd byte address, the
ILLOPA flag in register TFR is set and the CPU enters the illegal word operand access trap
routine. The IP value pushed onto the system stack is the address of the instruction following
the one which caused the trap.
6.9.10 Illegal instruction access trap
Whenever a branch is made to an odd byte address, the ILLINA flag in the TFR register is
set and the CPU enters the illegal instruction access trap routine. The IP value pushed onto
the system stack is the illegal odd target address of the branch instruction.
6.9.11 Illegal external bus access trap
Whenever the CPU requests an external instruction fetch, data read or data write, and no
external bus configuration has been specified, the ILLBUS flag in register TFR is set and the
CPU enters the illegal bus access trap routine. The IP value pushed onto the system stack is
the address of the instruction following the one which caused the trap. However, because the
ST10R262 is a romless microcontroller, an external bus must always be defined and this
trap should never occur.
