ST10R272L - EXTERNAL BUS INTERFACE
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pin WR serves as WRL (write low byte) and pin BHE serves as WRH (write high byte). Bit
WRCFG in register SYSCON selects the operating mode for pins WR and BHE. The
respective byte will be written on both data bus halves.
When reading bytes from an external 16-bit device, whole words may be read and the
ST10R272L automatically selects the byte to be input and discards the other. However, care
must be taken when reading devices that change state when being read, like FIFOs,
interrupt status registers, etc. In this case individual bytes should be selected using BHE and
A0.
PORT1 gets available for general purpose I/O, when none of the BUSCON registers selects
a demultiplexed bus mode.
9.2.5
Disable/enable control for pin BHE (BYTDIS)
Bit BYTDIS of SYSCON register controlls the active-low Byte High Enable (BHE) pin. The
BHE pin function is enabled if the BYTDIS bit contains a ’0’. Otherwise, it is disabled and the
pin can be used as standard I/O pin. The BHE pin is implicitly used by the External Bus
Controller to select one of two byte-organized memory chips which are connected to the
ST10R272L via a word-wide external data bus. After reset, the BHE function is automatically
enabled if a 16-bit data bus is selected during reset (BYTDIS = ’0’), otherwise it is disabled
(BYTDIS=’1’). It may be disabled if byte access to 16-bit memory is not required and the
BHE signal is not used.
9.2.6
Segment address generation
During external accesses the EBC generates a (programmable) number of address lines on
Port 4, which extend the 16-bit address output on PORT0 or PORT1, and so increase the
accessible address space. The number of segment address lines is selected during reset
and coded in bit field SALSEL in register RP0H (see table below).
Bus Mode
Transfer Rate
(Speed factor for byte/
word/dword access)
System Requirements
Free I/O
Lines
8-bit Multiplexed
Very low
(1.5 / 3 / 6)
Low (8-bit latch, byte bus)
P1H, P1L
8-bit Demultiplexed
Low
(1 / 2 / 4)
Very low (no latch, byte bus)
P0H
16-bit Multiplexed
High
(1.5 / 1.5 / 3)
High (16-bit latch, word bus)
P1H, P1L
16-bit Demultiplexed
Very high
(1 / 1 / 2)
Low (no latch, word bus)
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