ST10R272L - EXTERNAL BUS INTERFACE
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9.4
Controlling the external bus controller
A set of registers controls the EBC. General features like the use of interface pins (WR,
BHE), segmentation and internal ROM mapping are controlled by the SYSCON register. The
bus cycle properties such as chip select mode, the use of READY, length of ALE, external
bus mode, read/write delay and waitstates are controlled via registers
BUSCON4...BUSCON0. Four of these registers (BUSCON4...BUSCON1) have an
associated address select register (ADDRSEL4...ADDRSEL1) which specifies up to four
address areas and the individual bus characteristics within these areas. All accesses that
are not covered by these four areas are controlled via BUSCON0. This makes it possible to
use memory components or peripherals with different interfaces within the same system,
with optimized access.
Figure 61 Chip select delay
Normal CSx
RD
Address (P1)
ALE
Segment (P4)
Normal Demultiplexed
Bus Cycle
ALE Lengthen Demultiplexed
Bus Cycle
Unlatched CSx
WR
Read/Write
Delay
Data
Data
Data
Data
BUS (P0)
BUS (P0)
Read/Write
Delay
