ST10R272L - SYSTEM RESET
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Default: Emulation mode is off.
15.10.3 Adapt mode
When low during reset, Pin P0L.1 (ADP) selects the adapt mode. In this mode the
ST10R272L goes into a passive state, which is similar to its state during reset. The pins of
the ST10R272L float to tristate or are deactivated via internal pullup/pulldown devices, as
described for the reset state. In addition also the RSTOUT pin floats to tristate rather than be
driven low, and the on-chip oscillator is switched off.
This mode allows to switch a ST10R272L that is mounted to a board virtually off, so an
emulator may control the board’s circuitry, even though the original ST10R272L remains in
its place. The original ST10R272L also may resume to control the board after a reset
sequence with P0L.1 high.
Default: Adapt mode is off.
Note
When XTAL1 is fed by an external clock generator (while XTAL2 is left open), this
clock signal may also be used to drive the emulator device.
However, if a crystal is used, the emulator device’s oscillator can use this crystal
only, if at least XTAL2 of the original device is disconnected from the circuitry (the
output XTAL2 will still be active in Adapt Mode).
15.10.4 System clock configuration
Pins P0H.7 to P0H.5 (CLKSEL) selects the system clock configuration at reset. The system
clock (CPU Clock) can be selected to be 0.5, 1, 2, 2.5, 3, 4 or 5 times the externally applied
frequency at the XTAL-pins. The required system configuration setups are described in
“System clock generator” on page 17.
15.10.5 External bus type
Pins P0L.7 and P0L.6 (BUSTYP) select the external bus type during reset. This allows to
configure the external bus interface of the ST10R272L even for the first code fetch after
reset. The two bits are copied into bit field BTYP of register BUSCON0. P0L.7 controls the
data bus width, while P0L.6 controls the address output (multiplexed or demultiplexed). This
bit field may be changed via software after reset, if required.
PORT0 and PORT1 are automatically switched to the selected bus mode. In multiplexed bus
modes PORT0 drives both the 16-bit intra-segment address and the output data, while
PORT1 remains in high impedance state as long as no demultiplexed bus is selected via one
of the BUSCON registers. In demultiplexed bus modes PORT1 drives the 16-bit
intra-segment address, while PORT0 or P0L (according to the selected data bus width)
drives the output data.
For a 16-bit data bus BHE is automatically enabled, for an 8-bit data bus BHE is disabled via
bit BYTDIS in register SYSCON.
