ST10R272L - INTERRUPT AND TRAP FUNCTIONS
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When the interrupt request flag is set during the first CPU clock cycle of an instruction, the
minimum PEC response time is 4 CPU clock cycles.
The PEC response time is increased by all delays of the instructions in the pipeline that are
executed before starting the data transfer (including N).
•
When internal hold conditions between instruction pairs N-2/N-1 or N-1/N occur, the
minimum PEC response time may be extended by 1 CPU clock cycle for each of these
conditions.
•
Where instruction N reads the PSW, and instruction N-1 has an effect on the condition
flags, the PEC response time may additionally be extended by 2 CPU clock cycles.
Any reference to external locations increases the PEC response time due to pipeline related
access priorities. The following conditions must be considered:
•
Instruction fetch from an external location.
•
Operand read from an external location.
•
Result write-back to an external location.
Depending on where the instructions, source and destination operands are located, there are
a number of combinations. Note, however, that only access conflicts contribute to the delay.
The following examples illustrate these delays:
•
The worst case interrupt response time including external accesses will occur, when
instructions N and N+1 are executed out of external memory, instructions N-1 and N
require external operand read accesses and instructions N-3, N-2 and N-1 write back
Figure 24 Pipeline diagram for PEC response time
Pipeline Stage
Cycle 1
Cycle 2
Cycle 3
Cycle 4
FETCH
N
N + 1
N + 2
N + 2
DECODE
N - 1
N
PEC
N + 1
EXECUTE
N - 2
N - 1
N
PEC
WRITEBACK
N - 3
N - 2
N - 1
N
PEC Response Time
1
0
IR-Flag
