ST10R272L - INTERRUPT AND TRAP FUNCTIONS
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The following table shows - in a few examples - where an action is triggered by the
programming of an interrupt control register.
Note
All requests on levels 13...1 cannot initiate PEC transfers. They are always serviced
by an interrupt service routine. No PECC register is associated and no COUNT
field is checked.
6.1.5
Interrupt control functions in the PSW
The Processor Status Word (PSW) is divided into 2 functional parts: the lower byte of the
PSW represents the arithmetic status of the CPU, the upper byte of the PSW controls the
Figure 20 Priority levels and PEC channels
Priority Level
Type of Service
ILVL
GLVL
COUNT = 00h
COUNT
≠
00h
1 1 1 1
1 1
CPU interrupt, level 15, group priority 3
PEC service, channel 7
1 1 1 1
1 0
CPU interrupt, level 15, group priority 2
PEC service, channel 6
1 1 1 0
1 0
CPU interrupt, level 14, group priority 2
PEC service, channel 2
1 1 0 1
1 0
CPU interrupt, level 13, group priority 2
CPU interrupt level 13, group priority 2
0 0 0 1
1 1
CPU interrupt, level 1, group priority 3
CPU interrupt level 1, group priority 3
0 0 0 1
0 0
CPU interrupt, level 1, group priority 0
CPU interrupt level 1, group priority 0
0 0 0 0
X X
No service!
No service!
Table 14 Triggering an action with the interrupt control register (examples)
ILVL
GLVL
PEC channel
PEC Control
interrupt control register
