ST10R272L - EXTERNAL BUS INTERFACE
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When the READY or READY function is enabled for a specific address window, each bus
cycle in this window must be terminated with the active level defined by the RDYPOL bit 13
in the associated BUSCON register.
The READY/READY function is enabled by the RDYENx bits in the BUSCON registers.
When this function is selected (RDYENx = ‘1’), only the lower 3 bits of the respective MCTC
bit field define the number of inserted waitstates (0...7), while the MSB of bit field MCTC
selects the READY operation:
MCTC.3 = ‘0’: Synchronous READY/READY, i.e. the READY/READY signal must meet setup
and hold times. MCTC.3 = ‘1’: Asynchronous READY/READY, i.e. the READY/READY signal
is synchronized internally.
The Synchronous READY/READY provides the fastest bus cycles, but requires setup and
hold times to be met. The CLKOUT signal should be enabled and may be used by the
peripheral logic to control the READY/READY timing in this case.
The Asynchronous READY/READY is less restrictive, but requires additional waitstates
caused by the internal synchronization. As the asynchronous READY/READY is sampled
earlier (see figure above) programmed waitstates may be necessary to provide proper bus
cycles (see also notes on “normally-ready” peripherals below).
Figure 60 READY/READY controlled bus cycles
ALE
RD/WR
SREADY
AREADY
SREADY
AREADY
Bus Cycle with active READY or READY
Bus Cycle Extended via READY or READY
1.WS
2.WS
1.WS
2.WS
:Evaluation (sampling) of the READY/READY input
