ST10R272L - GENERAL PURPOSE TIMER UNITS
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Auxiliary timer in capture mode
Capture mode for the auxiliary timers T2 and T4 is selected by setting bit field TxM in the
respective register TxCON to ‘101
B
’. In capture mode the contents of the core timer are
latched into an auxiliary timer register in response to a signal transition at the respective
auxiliary timer's external input pin TxIN. The capture trigger signal can be a positive, a
negative, or both a positive and a negative transition.
The two least significant bits of bit field TxI are used to select the active transition (see table
in the counter mode section), while the most significant bit TxI.2 is irrelevant for capture
mode. It is recommended to keep this bit cleared (TxI.2 = ‘0’).
Note
When programmed for capture mode, the respective auxiliary timer (T2 or T4)
stops independent of its run flag T2R or T4R.
Upon a trigger (selected transition) at the corresponding input pin TxIN the contents of the
core timer are loaded into the auxiliary timer register and the associated interrupt request
flag TxIR will be set.
Note
The direction control bits DP3.7 (for T2IN) and DP3.5 (for T4IN) must be set to ’0’,
and the level of the capture trigger signal should be held high or low for at least 8
CPU clock cycles before it changes to ensure correct edge detection.
11.1.3 Interrupt control for GPT1 timers
When a timer overflows from FFFF
H
to 0000
H
(when counting up), or when it underflows
from 0000
H
to FFFF
H
(when counting down), its interrupt request flag (T2IR, T3IR or T4IR)
Figure 81 GPT1 auxiliary timer in capture mode
