ST10R272L - EXTERNAL BUS INTERFACE
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Internal accesses are executed with maximum speed and therefore are not programmable.
External accesses use the slowest possible bus cycle after reset. The bus cycle timing may
then be optimized by the initialization software.
9.3.1
ALE length control
The length of the ALE signal and the address hold time after its falling edge are controlled by
the ALECTLx bits in the BUSCON registers. When bit ALECTL is set to ‘1’, external bus
cycles accessing the respective address window will have their ALE signal prolonged by half
a CPU clock. Also the address hold time after the falling edge of ALE (on a multiplexed bus)
will be prolonged by half a CPU clock, so the data transfer within a bus cycle refers to the
same CLKOUT edges as usual (i.e. the data transfer is delayed by one CPU clock). This
allows more time for the address to be latched.
Figure 55 Programmable external bus cycle
