ST10R272L - SYNCHRONOUS SERIAL PORT
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While SSPTB0 must be the last transmit buffer register written, there are no sequence
requirment for writing to the other two SSPTBx registers. SSPTB2 can be written prior to
SSPTB1 or vice versa. The following table shows the SSP operation as a function of which
transmit buffer registers are written, prior to a transfer.
Figure 101 Write operation controlled through transmit buffer full signal
Transmit Buffers written
Transfer length
Transfer sequence
SSPTB2, SSPTB1, SSPTB0
24-bit (3 byte) transfer
SSPTB2, SSPTB1, SSPTB0
SSPTB1, SSPTB2, SSPTB0
24-bit (3 Byte) transfer
SSPTB2, SSPTB1, SSPTB0
SSPTB1, SSPTB0
16-bit (2 byte) transfer
SSPTB1, SSPTB0
SSPTB2, SSPTB0
illegal option
-
SSPTB0
8-bit (1 byte) transfer
SSPTB0
Table 41 SSP operation as a function of transmit buffer registers
SSPCLK
SSPDAT
SSPCE0, 1
TB2
Full
23
22
17
VR02084C
Byte 0
Byte 1
Byte 2
16 15 14
9
8
7
6
1
0
TB1
Full
TB0
Full
Write
TB0
Write
TB1
Write
TB2
