ST10R272L - EXTERNAL BUS INTERFACE
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the ST10R272L needs access to the shared resources and demands this by activating its
BREQ output. The arbitration logic may then deactivate the other master’s HLDA and so free
the external bus for the ST10R272L, depending on the priority of the different masters.
Note
The falling BREQ edge shows the last chance for BREQ to trigger the indicated
regain-sequence. Even if BREQ is activated earlier the regain-sequence is initiated
by HOLD going high. BREQ and HOLD are connected via an external arbitration
circuitry. Please note that HOLD may also be deactivated without the ST10R272L
requesting the bus.
9.7
The XBUS interface
The ST10R272L provides an on-chip interface (the XBUS interface), which allows to connect
integrated customer/application specific peripherals to the standard controller core. The
XBUS is an internal representation of the external bus interface, i.e. it is operated in the
same way.
The current XBUS interface is prepared to support up to 3 X-Peripherals.
For each peripheral on the XBUS (X-Peripheral) there is a separate address window
controlled by an XBCON and an XADRS register. As an interface to a peripheral in many
cases is represented by just a few registers, the XADRS registers select smaller address
windows than the standard ADDRSEL registers. As the register pairs control integrated
peripherals rather than externally connected ones, they are fixed by mask programming
rather than being user programmable.
Figure 63 External bus arbitration - regaining the bus
