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Write cycles: The command signal is now deactivated. The data remain valid on the bus
until the next external bus cycle is started.
9.2.2
Demultiplexed bus modes
In the demultiplexed bus modes the 16-bit intra-segment address is permanently output on
PORT1, while the data uses PORT0 (16-bit data) or P0L (8-bit data).
The upper address lines are permanently output on Port 4 (if selected via SALSEL during
reset). No address latches are required.
The EBC initiates an external access by placing an address on the address bus. After a
programmable period of time the EBC activates the respective command signal (RD, WR,
WRL, WRH). Data is driven onto the data bus either by the EBC (for write cycles) or by the
external memory/peripheral (for read cycles). After a period of time, which is determined by
the access time of the memory/peripheral, data become valid.
Read cycles: Input data is latched and the command signal is now deactivated. This causes
the accessed device to remove its data from the data bus which is then tri-stated again.
Figure 52 Multiplexed bus cycle
