ST10R272L - EXTERNAL BUS INTERFACE
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Note
The total accessible address space may be increased by accessing several banks
which are distinguished by individual chip select signals.
9.2.7 CS signal generation
During external accesses the EBC can generate a (programmable) number of CS lines on
Port 6, which allow to directly select external peripherals or memory banks without requiring
an external decoder. The number of CS lines is selected during reset and coded in bit field
CSSEL in register RP0H.
The CSx outputs are associated with the BUSCONx registers and are driven active (low) for
any access within the address area defined for the respective BUSCON register. For any
access outside this defined address area the respective CSx signal will go inactive (high).
Note
No CSx signal will be generated for an access to any internal address area, even if
this area is covered by the respective ADDRSELx register.
SALSEL
Segment Address
Lines
Directly accessible Address Space
1 1
Two:
A17...A16
256
KByte (default without pulldowns)
1 0
Eight:
A23...A16
16
MByte (max.)
0 1
None
64
KByte (min.)
0 0
Four:
A19...A16
1
MByte
Table 25 Address segmentation
CSSEL
Chip Select Lines
Note
1 1
Five:
CS4...CS0
Default without pull-downs
1 0
None
Port 6 pins free for I/O
0 1
Two:
CS1...CS0
0 0
Three:
CS2...CS0
Table 26 Bitfield CSEL in RPOH register
