ST10R272L - PARALLEL PORTS
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of the output latch. A read-modify-write operation reads the value of the output latch,
modifies it, and writes it back to the output latch, thus also modifying the level at the pin.
Note
E denotes an ESFR located in the ESFR space
In the ST10R272L certain ports provide Open Drain Control, which allows to switch the
output driver of a port pin from a push/pull configuration to an open drain configuration. In
push/pull mode a port output driver has an upper and a lower transistor, thus it can actively
drive the line either to a high or a low level. In open drain mode the upper transistor is always
switched off, and the output driver can only actively drive the line to a low level. When writing
a ‘1’ to the port latch, the lower transistor is switched off and the output enters a
high-impedance state. The high level must then be provided by an external pullup device.
With this feature, it is possible to connect several port pins together to a Wired-AND
configuration, saving external glue logic and/or additional software overhead for enabling/
disabling output signals.
This feature is implemented for ports P2, P3 and P6 (see respective sections), and is
controlled through the respective Open Drain Control Registers ODPx. These registers allow
the individual bit-wise selection of the open drain mode for each port line. If the respective
control bit ODPx.y is ‘0’ (default after reset), the output driver is in the push/pull mode. If
ODPx.y is ‘1’, the open drain configuration is selected. Note that all ODPx registers are
located in the ESFR space.
Figure 25 SFRs and pins associated with the parallel ports
ODP2
DP2
P5
P2
P6
DP6
ODP6
P0L
P0H
DP0L
DP0H
P4
P1L
P1H
P3
DP3
DP4
DP1H
DP1L
ODP3
Data input/output
registers
Direction control
registers
Open drain control
registers
E
E
E
E
E
E
E
P7
