ST10R272L - SYNCHRONOUS SERIAL PORT
244/320
Reserved Byte (00’EF07h)
Reset Value: xxh
SSPTB2 (00’EF06h)
Reset Value: xxh
SSPTB1 (00’EF05h)
Reset Value: xxh
SSPTB0 (00’EF04h)
Reset Value: xxh
13.2.4 Initialization
After reset, all SSP I/O lines are in high-impedance state. The SSPDAT line is controlled
automatically by the SSP, according to the performed read or write operation. The SSPCLK,
SSPCE0 and SSPCE1 lines, however, have individual output control bits. This allows the
user to first program the desired polarity of these lines before switching them to output. With
this, it is possible to pull the lines to the desired initial polarity already during and after rest
until they are switched to push/pull outputs by connecting external pullup or pulldown
resistors to pins.
While the polarity of the chip enables lines is programmed via register SSPCON1, the
polarity of the clock line is controlled through a bit in register SSPCON0. The reason for this
is that the chip enable polarity normally only needs to be selected during initialization, while
the clock line polarity and active edge might be switched between transfers to different
peripheral slaves. This can be handled by a write to only one control register, SSPCON0,
together with other necessary selections for the transfer.
13.2.5 Starting a transfer
Prior to any transfer, all required selections for this transfer should be made. This is
performed through programming the control bits in SSPCON0 register to the desired values.
The SSPCKS0..2 bits determine the baudrate of the transfer. With the SSPCKS1..0 bits, the
appropriate chip enable line(s) is (are) selected. If a continuous transfer is desired, bit
SSPCM must be set. The heading control bit SSPHB selects whether each byte is
transferred with LSB or MSB first. The type of operation, a read or write operation, is
controlled through bit SSPRW. If set, a read operation will take place. In order to
communicate with several peripherals with different clocking requirements, the control bits
SSPCKP and SSPCKE allow to set the polarity and relevant shift/latch edges of the clock.
5
4
3
2
1
0
11
10
9
8
7
6
15
14
13
12
rw
-
TRANSMIT BYTE 2
reserved
5
4
3
2
1
0
11
10
9
8
7
6
15
14
13
12
rw
rw
RECEIVE/TRANSMIT BYTE 0
TRANSMIT BYTE 1
