ST10R272L - ASYNCHRONOUS/SYNCHRONOUS SERIAL INTERFACE
232/320
P3.10 outputs the shift clock. These signals are alternate functions of Port 3 pins.
Synchronous mode is selected with S0M=’000b’.
8 data bits are transmitted or received synchronous to a shift clock generated by the internal
baud rate generator. The shift clock is only active as long as data bits are transmitted or
received.
Synchronous transmission begins within 4 CPU clock cycles after data has been loaded
into S0TBUF, provided that S0R is set and S0REN=’0’ (half-duplex, no reception). Data
transmission is double buffered. When the transmitter is idle, the transmit data loaded into
S0TBUF is immediately moved to the transmit shift register, thus freeing S0TBUF for the
next data to be sent. This is indicated by the transmit buffer interrupt request flag S0TBIR
being set. S0TBUF may now be loaded with the next data while transmission of the previous
one is still going on. The data bits are transmitted synchronously with the shift clock. After
the bit time for the 8th data bit, both pins TXD0 and RXD0 will go high, the transmit interrupt
request flag S0TIR is set, and serial data transmission stops.
Figure 95 Synchronous mode of serial channel ASC0
