ST10R272L - GENERAL PURPOSE TIMER UNITS
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to these 3 counting modes, the auxiliary timer can be concatenated with the core timer. The
auxiliary timer has no output toggle latch and no alternate output function.
The individual configuration for timer T5 is determined by its bitaddressable control register
T5CON. Note that functions which are present in both timers of block GPT2 are controlled in
the same bit positions and in the same manner in each of the specific control registers.
T5CON (FF46h / A3h)
SFR
Reset Value: 0000h
Bit
Function
T5I
Timer 5 Input Selection
Depends on the Operating Mode, see respective sections.
T5M
Timer 5 Mode Control (Basic Operating Mode)
0 0: Timer Mode
0 1: Counter Mode
1 0: Gated Timer with Gate active low
1 1: Gated Timer with Gate active high
T5R
Timer 5 Run Bit
T5R = ‘0’: Timer / Counter 5 stops
T5R = ‘1’: Timer / Counter 5 runs
T5UD
Timer 5 Up / Down Control
1
T5UDE
Timer 5 External Up/Down Enable
1
CI
Register CAPREL Input Selection
0 0: Capture disabled
0 1: Positive transition (rising edge) on CAPIN
1 0: Negative transition (falling edge) on CAPIN
1 1: Any transition (rising or falling edge) on CAPIN
T5CLR
Timer 5 Clear Bit
T5CLR = ‘0’: Timer 5 not cleared on a capture
T5CLR = ‘1’: Timer 5 is cleared on a capture
5
4
3
2
1
0
11
10
9
8
7
6
15
14
13
12
-
rw
rw
-
-
-
rw
rw
rw
rw
rw
rw
T5I
-
T5R
T5UD
-
T5
UDE
T5M
T5
CLR
CI
-
CT3
T5SC
