ST10R272L - INTERRUPT AND TRAP FUNCTIONS
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EXICON (F1C0h / E0h)
ESFR
Reset Value: 0000h
CCxIC (seeTable 19)
SFR
Reset Value: --00h
Note
The fast external interrupt inputs are sampled every CPU clock cycle. The interrupt
request arbitration and processing, however, is executed every 4 CPU clock cycles.
Bit
Function
EXIxES
External Interrupt x Edge Selection Field (x=3...0)
0 0: Fast external interrupts disabled: standard mode
0 1: Interrupt on positive edge (rising)
1 0: Interrupt on negative edge (falling)
1 1: Interrupt on any edge (rising or falling)
Register
Address
Reg. Space
CC8IC
FF88
H
/C4
H
SFR
CC9IC
FF8A
H
/C5
H
SFR
CC10IC
FF8C
H
/C6
H
SFR
CC11IC
FF8E
H
/C7
H
SFR
CC12IC
FF90
H
/C8
H
SFR
CC13IC
FF92
H
/C9
H
SFR
CC14IC
FF94
H
/CA
H
SFR
CC15IC
FF96
H
/CB
H
SFR
Table 19 External interrupt control registers
5
4
3
2
1
0
7
6
rw
rw
rw
EXI2ES
EXI0ES
EXI1ES
rw
EXI3ES
5
4
3
2
1
0
11
10
9
8
7
6
15
14
13
12
rw
rw
rw
CCx
IE
GLVL
-
-
-
rw
-
CCx
IR
-
-
-
-
ILVL
