ST10R272L - INTERRUPT AND TRAP FUNCTIONS
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external operands. In this case the PEC response time is the time to perform 7 word bus
accesses.
•
When instructions N and N+1 are executed out of external memory, but all operands for
instructions N-3 through N-1 are in internal memory, then the PEC response time is the
time to perform 1 word bus access plus 2 CPU clock cycles.
Once a request for PEC service has been acknowledged by the CPU, the execution of the
next instruction is delayed by 2 CPU clock cycles, plus any additional time it takes to fetch
the source operand from external memory and to write the destination operand over the
external bus in an external program environment.
Note
A bus access in this context also includes delays caused by an external READY
signal or by bus arbitration (HOLD mode).
6.8
External interrupts
Although the ST10R272L has no dedicated INTR input pins, it can react to external
asynchronous events by using the IO lines for interrupt input. The interrupt function can be
combined with the pin’s main function or can be used instead of it, i.e. if the main pin function
is not required.
Interrupt signals may be connected to:
•
T4IN, T2IN, the timer input pins
•
CAPIN, the capture input of GPT2
For each of these pins, either a positive, a negative, or both a positive and a negative
external transition can be selected to cause an interrupt or PEC service request. The edge
selection is performed in the control register of the peripheral device associated with the
respective port pin. The peripheral must be programmed to a specific operating mode to
generate an interrupt with the external signal. The priority of the interrupt request is
determined by the interrupt control register of the peripheral interrupt source, and the
interrupt vector of this source will be used to service the external interrupt request.
Note
To use a listed pin as external interrupt input, it must be switched to input mode via
its direction control bit DPx.y in the port direction control register DPx.
Pins T2IN or T4IN can be used as external interrupt input pins when the associated auxiliary
timer T2 or T4 in block GPT1 is configured for capture mode. This mode is selected by
programming the mode control fields T2M or T4M in control registers T2CON or T4CON to
101b. The active edge of the external input signal is determined by bit fields T2I or T4I.
When these fields are programmed to X01b, Interrupt Request Flags T2IR or T4IR in
registers T2IC or T4IC will be set on a positive external transition at pins T2IN or T4IN,
respectively. When T2I or T4I are programmed to X10b, then a negative external transition
will set the corresponding request flag. When T2I or T4I are programmed to X11b, both a
