ST10R272L - EXTERNAL BUS INTERFACE
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Note
BUSACT0 is initialized with 0, if pin EA is high during reset. If pin EA is low during
reset, bit BUSACT0 is set. ALECTL0 is set (‘1’) and bit field BTYP is loaded with the
bus configuration selected via PORT0.
MTTCx
Memory Tristate Time Control
‘0’: 1 waitstate
‘1’: No waitstate
BTYPx
External Bus Configuration
0 0: 8-bit Demultiplexed Bus
0 1: 8-bit Multiplexed Bus
1 0: 16-bit Demultiplexed Bus
1 1: 16-bit Multiplexed Bus
Note: For BUSCON0 BTYP is defined via PORT0 during reset.
ALECTLx
ALE Lengthening Control
‘0’: Normal ALE signal
‘1’: Lengthened ALE signal
BUSACTx
Bus Active Control
‘0’: External bus disabled
‘1’: External bus enabled (within the respective address window, see ADDRSEL)
RDYENx
READY Input Enable
‘0’: External bus cycle is controlled by bit field MCTC only
‘1’: External bus cycle is controlled by the READY input signal
RDYPOLx
Ready Active Level Control
‘0’: The active level on the READY pin is low, bus cycle terminates with a ‘0’ on READY
pin,
‘1’: The active level on the READY pin is high, bus cycle terminates with a ‘1’ on
READY pin.
CSRENx
Read Chip Select Enable
‘0’: The CS signal is independent of the read command (RD)
‘1’: The CS signal is generated for the duration of the read command
CSWENx
Write Chip Select Enable
‘0’: The CS signal is independent of the write command (WR,WRL,WRH)
‘1’: The CS signal is generated for the duration of the write command
Bit
Function
