ST10R272L - EXTERNAL BUS INTERFACE
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PORT1 will output the intra-segment address, when any of the BUSCON registers selects a
demultiplexed bus mode, even if the current bus cycle uses a multiplexed bus mode. This
allows to have an external address decoder connected to PORT1 only, while using it for all
kinds of bus cycles.
Note: Never change the configuration for an address area that currently supplies the
instruction stream. Due to the internal pipelining it is very difficult to determine the first
instruction fetch that will use the new configuration. Only change the configuration for
address areas that are not currently accessed. This applies to BUSCON registers as well as
to ADDRSEL registers.
The usage of the BUSCON/ADDRSEL registers is controlled via the issued addresses.
When an access (code fetch or data) is initiated, the respective generated physical address
defines, if the access is made internally, uses one of the address windows defined by
ADDRSEL4...1, or uses the default configuration in BUSCON0. After initializing the active
registers, they are selected and evaluated automatically by interpreting the physical
address. No additional switching or selecting is necessary during run time, except when
more than the four address windows plus the default is to be used.
Switching from demultiplexed to multiplexed bus mode represents a special case. The
bus cycle is started by activating ALE and driving the address to Port 4 and PORT1 as usual,
if another BUSCON register selects a demultiplexed bus. However, in the multiplexed bus
modes the address is also required on PORT0. In this special case the address on PORT0
is delayed by one CPU clock cycle, which delays the complete (multiplexed) bus cycle and
extends the corresponding ALE signal (see figure below).
