ST10R272L - INTERRUPT AND TRAP FUNCTIONS
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Note
The TRAP instruction does not change the CPU level, therefore, software invoked
trap service routines may be interrupted by higher requests.
Interrupt Enable bit IEN globally enables or disables PEC operation and the acceptance of
interrupts by the CPU. When IEN is cleared, no interrupt requests are accepted by the CPU.
When IEN is set to ’1’, all interrupt sources which are enabled by the interrupt enable bits in
the control registers, are globally enabled.
Note
Traps are non-maskable and are not affected by the IEN bit.
6.2
Operation of the PEC channels
The Peripheral Event Controller (PEC) has 8 PEC service channels which move a single
byte or word between two locations in segment 0 (data pages 3...0). This is the fastest
possible interrupt response and in many cases is sufficient to service a peripheral request
(e.g. serial channels, etc.). Each channel is controlled by a dedicated PEC Channel Counter/
Control register (PECCx) and a pair of pointers (for source (SRCPx) and destination
(DSTPx) of t
he d
ata transfer).
The PECC registers control the PEC channel.
PECCx (FECyh/6Zh Table 15)
SFR
Reset Value: 0000h
Bit
Function
COUNT
PEC Transfer Count
Counts PEC transfers and influences the channel’s action (see table below)
BWT
Byte / Word Transfer Selection
0: Transfer a Word
1: Transfer a Byte
INC
Increment Control (Modification of SRCPx or DSTPx)
0 0: Pointers are not modified
0 1: Increment DSTPx by 1 or 2 (BWT)
1 0: Increment SRCPx by 1 or 2 (BWT)
1 1: Reserved. Do not use this combination. (changed to 10 by hardware)
-
-
5
4
3
2
1
0
11
10
9
8
7
6
15
14
13
12
rw
rw
rw
-
BWT
-
-
-
-
-
-
-
INC
COUNT
